X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=4361b1a1561dd922fa6cff8dc364dafb507d5dbe;hb=b06b80dccdf4e71b37866cc0e32a800a2b1a62d1;hp=2459b75324854f97a3266db410820fc432f2bcc3;hpb=29226701a8ca7a5754b3d52cd9e99cf588782a75;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 2459b75..4361b1a 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -3,18 +3,14 @@ package sifive.blocks.devices.spi
 
 import Chisel._
 import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksBundle,
-  HasTopLevelNetworksModule
-}
-import uncore.tilelink2.{TLFragmenter, TLWidthWidget}
+import diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import rocketchip.HasSystemNetworks
+import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
 import util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
-trait HasPeripherySPI extends HasTopLevelNetworks {
+trait HasPeripherySPI extends HasSystemNetworks {
   val spiParams = p(PeripherySPIKey)  
   val spis = spiParams map { params =>
     val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
@@ -24,22 +20,28 @@ trait HasPeripherySPI extends HasTopLevelNetworks {
   }
 }
 
-trait HasPeripherySPIBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripherySPI
-  val spis = HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))
+trait HasPeripherySPIBundle {
+  val spis: HeterogeneousBag[SPIPortIO]
+
+  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
+    val pin = Module(new SPIGPIOPort(s.c, syncStages))
+    pin.io.spi <> s
+    pin
+  }
 }
 
-trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
+trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
   val outer: HasPeripherySPI
-  val io: HasPeripherySPIBundle
-  (io.spis zip outer.spis).foreach { case (io, device) =>
+  val spis = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
+
+  (spis zip outer.spis).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
 
 case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait HasPeripherySPIFlash extends HasTopLevelNetworks {
+trait HasPeripherySPIFlash extends HasSystemNetworks {
   val spiFlashParams = p(PeripherySPIFlashKey)  
   val qspi = spiFlashParams map { params =>
     val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
@@ -50,17 +52,16 @@ trait HasPeripherySPIFlash extends HasTopLevelNetworks {
   }
 }
 
-trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripherySPIFlash 
-  val qspi = HeterogenousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
+trait HasPeripherySPIFlashBundle {
+  val qspi: HeterogeneousBag[SPIPortIO]
 }
 
-trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
+trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
   val outer: HasPeripherySPIFlash
-  val io: HasPeripherySPIFlashBundle
+  val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
 
-  (io.qspi zip outer.qspi) foreach { case (io, device) => 
-    io.qspi <> device.module.io.port
+  (qspi zip outer.qspi) foreach { case (io, device) => 
+    io <> device.module.io.port
   }
 }