X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=4361b1a1561dd922fa6cff8dc364dafb507d5dbe;hb=b06b80dccdf4e71b37866cc0e32a800a2b1a62d1;hp=bd77259dad2577e205c3e13b371c0699f88c14c2;hpb=7c118790cb89a74d8a67d8d1f78fe07b5a71038e;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index bd77259..4361b1a 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -23,8 +23,8 @@ trait HasPeripherySPI extends HasSystemNetworks {
 trait HasPeripherySPIBundle {
   val spis: HeterogeneousBag[SPIPortIO]
 
-  def SPItoGPIOPins(sync_stages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
-    val pin = Module(new SPIGPIOPort(s.c, sync_stages))
+  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
+    val pin = Module(new SPIGPIOPort(s.c, syncStages))
     pin.io.spi <> s
     pin
   }