X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=dd76d15db4df1ca8149bef39a53c55f0b8cb2478;hb=90e6ea1d2da7114ade389cc43d82ae202bc18007;hp=b2edb0f64f14d2f9009af8d34cfbc56d6992a953;hpb=e4960a4e5a5572ff90ce8c682e945d04d8dc6b0d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index b2edb0f..dd76d15 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -41,10 +41,10 @@ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
   val qspis = spiFlashParams map { params =>
     val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
     qspi.rnode := pbus.toVariableWidthSlaves
-    qspi.fnode :=
-      TLFragmenter(1, pbus.blockBytes)(
-      TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)(
-      pbus.toFixedWidthSlaves))
+    (qspi.fnode
+      := TLFragmenter(1, pbus.blockBytes)
+      := TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
+      := pbus.toFixedWidthSlaves)
     ibus.fromSync := qspi.intnode
     qspi
   }