X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=f95be7e51fb43535868dc2ccb7ad38903876200b;hb=4d74e8f67f871df93f7bb2dfb2fa8bffb641fc4a;hp=4361b1a1561dd922fa6cff8dc364dafb507d5dbe;hpb=b06b80dccdf4e71b37866cc0e32a800a2b1a62d1;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 4361b1a..f95be7e 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -2,11 +2,11 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
@@ -23,11 +23,6 @@ trait HasPeripherySPI extends HasSystemNetworks {
 trait HasPeripherySPIBundle {
   val spis: HeterogeneousBag[SPIPortIO]
 
-  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
-    val pin = Module(new SPIGPIOPort(s.c, syncStages))
-    pin.io.spi <> s
-    pin
-  }
 }
 
 trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
@@ -54,6 +49,7 @@ trait HasPeripherySPIFlash extends HasSystemNetworks {
 
 trait HasPeripherySPIFlashBundle {
   val qspi: HeterogeneousBag[SPIPortIO]
+
 }
 
 trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {