X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=f95be7e51fb43535868dc2ccb7ad38903876200b;hb=4d74e8f67f871df93f7bb2dfb2fa8bffb641fc4a;hp=bdd74c66a041e8aaa80f90df21c3855768015361;hpb=03be9aba67b185b5454e9013901e6f873f62ac9d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index bdd74c6..f95be7e 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -2,56 +2,62 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import diplomacy.LazyModule
-import uncore.tilelink2._
-import rocketchip.{TopNetwork,TopNetworkModule}
-import util.HeterogeneousBag
-
-trait PeripherySPI {
-  this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
-  val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
-    val spi = LazyModule(new TLSPI(c))
-    spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+import freechips.rocketchip.util.HeterogeneousBag
+
+case object PeripherySPIKey extends Field[Seq[SPIParams]]
+
+trait HasPeripherySPI extends HasSystemNetworks {
+  val spiParams = p(PeripherySPIKey)  
+  val spis = spiParams map { params =>
+    val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
+    spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := spi.intnode
     spi
   }
 }
 
-trait PeripherySPIBundle {
-  this: { val spiConfigs: Seq[SPIConfig] } =>
-  val spis = HeterogeneousBag(spiConfigs.map(new SPIPortIO(_)))
+trait HasPeripherySPIBundle {
+  val spis: HeterogeneousBag[SPIPortIO]
+
 }
 
-trait PeripherySPIModule {
-  this: TopNetworkModule {
-    val spiConfigs: Seq[SPIConfig]
-    val outer: PeripherySPI
-    val io: PeripherySPIBundle
-  } =>
-  (io.spis zip outer.spi).foreach { case (io, device) =>
+trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
+  val outer: HasPeripherySPI
+  val spis = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
+
+  (spis zip outer.spis).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
 
+case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait PeripherySPIFlash {
-  this: TopNetwork { val spiFlashConfig: SPIFlashConfig } =>
-  val qspi = LazyModule(new TLSPIFlash(spiFlashConfig))
-  qspi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
-  qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
-  intBus.intnode := qspi.intnode
+trait HasPeripherySPIFlash extends HasSystemNetworks {
+  val spiFlashParams = p(PeripherySPIFlashKey)  
+  val qspi = spiFlashParams map { params =>
+    val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
+    qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
+    qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
+    intBus.intnode := qspi.intnode
+    qspi
+  }
 }
 
-trait PeripherySPIFlashBundle {
-  this: { val spiFlashConfig: SPIFlashConfig } =>
-  val qspi = new SPIPortIO(spiFlashConfig)
+trait HasPeripherySPIFlashBundle {
+  val qspi: HeterogeneousBag[SPIPortIO]
+
 }
 
-trait PeripherySPIFlashModule {
-  this: TopNetworkModule {
-    val spiConfigs: Seq[SPIConfig]
-    val outer: PeripherySPIFlash
-    val io: PeripherySPIFlashBundle
-  } =>
-  io.qspi <> outer.qspi.module.io.port
+trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
+  val outer: HasPeripherySPIFlash
+  val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
+
+  (qspi zip outer.qspi) foreach { case (io, device) => 
+    io <> device.module.io.port
+  }
 }
+