X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPhysical.scala;h=802233da97db14f3509888de204da26a7446bd95;hb=baccd5ada2ab54381d9f4c75a3e3e72f39b2bcef;hp=cb26bc99046e3dbeb273b376e397b31c611b5567;hpb=03be9aba67b185b5454e9013901e6f873f62ac9d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index cb26bc9..802233d 100644
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.spi
 import Chisel._
 import sifive.blocks.util.ShiftRegisterInit
 
-class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
+class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
   val fn = Bits(width = 1)
   val stb = Bool()
   val cnt = UInt(width = c.countBits)
@@ -16,12 +16,12 @@ object SPIMicroOp {
   def Delay    = UInt(1, 1)
 }
 
-class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {
+class SPIPhyControl(c: SPIParamsBase) extends SPIBundle(c) {
   val sck = new SPIClocking(c)
   val fmt = new SPIFormat(c)
 }
 
-class SPIPhysical(c: SPIConfigBase) extends Module {
+class SPIPhysical(c: SPIParamsBase) extends Module {
   val io = new SPIBundle(c) {
     val port = new SPIPortIO(c)
     val ctrl = new SPIPhyControl(c).asInput