X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPins.scala;h=346f8ee63d820e6fae8436858332b06ebe0b04a8;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hp=48c302070c1fe0a882fa49b6b3e97f2aacd53fc9;hpb=7916ef5249c72a3a84c599d123760f4d716de58a;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index 48c3020..346f8ee 100644
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -2,33 +2,31 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
+import chisel3.experimental.{withClockAndReset}
+import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
-class SPIPinsIO(c: SPIConfigBase) extends SPIBundle(c) {
-  val sck = new GPIOPin
-  val dq = Vec(4, new GPIOPin)
-  val cs = Vec(c.csWidth, new GPIOPin)
-}
+class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
 
-class SPIGPIOPort(c: SPIConfigBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
-  val io = new SPIBundle(c) {
-    val spi = new SPIPortIO(c).flip
-    val pins = new SPIPinsIO(c)
-  }
+  val sck: T      = pingen()
+  val dq: Vec[T]  = Vec(4, pingen())
+  val cs: Vec[T]  = Vec(c.csWidth, pingen())
 
-  GPIOOutputPinCtrl(io.pins.sck, io.spi.sck, ds = driveStrength)
+  def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
+    syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
-  GPIOOutputPinCtrl(io.pins.dq, Bits(0, io.spi.dq.size))
-  (io.pins.dq zip io.spi.dq).foreach {
-    case (p, s) =>
-      p.o.oval := s.o
-      p.o.oe  := s.oe
-      p.o.ie  := ~s.oe
-      p.o.pue := Bool(true)
-      p.o.ds  := driveStrength
-      s.i := ShiftRegister(p.i.ival, syncStages)
-  }
+    withClockAndReset(clock, reset) {
+      sck.outputPin(spi.sck, ds = driveStrength)
 
-  GPIOOutputPinCtrl(io.pins.cs, io.spi.cs.asUInt)
-  io.pins.cs.foreach(_.o.ds := driveStrength)
+      (dq zip spi.dq).foreach {case (p, s) =>
+        p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
+        p.o.oe := s.oe
+        p.o.ie := ~s.oe
+        s.i := ShiftRegister(p.i.ival, syncStages)
+      }
+
+      (cs zip spi.cs) foreach { case (c, s) =>
+        c.outputPin(s, ds = driveStrength)
+      }
+    }
+  }
 }