X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=00e5fdd856e5003fda3062050b8fe172a07d85f0;hb=015f87ec6b355c0876955b174d5b64300569d68d;hp=d42850f88eca4388a571ac86e47743c69406beef;hpb=0a80d1987d35046858c36a4fa462410b54a126f0;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index d42850f..00e5fdd 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.uart
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
 import sifive.blocks.util.ShiftRegisterInit
@@ -12,7 +12,8 @@ import sifive.blocks.util.ShiftRegisterInit
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
 trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
-  val uartParams = p(PeripheryUARTKey)  
+  private val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
+  val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
   val uarts = uartParams map { params =>
     val uart = LazyModule(new TLUART(pbus.beatBytes, params))
     uart.node := pbus.toVariableWidthSlaves
@@ -46,7 +47,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 
-  def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+  def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()