X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=01ae55cd9ea18d47401e71ab0c6a94e3b3bd1c48;hb=4381e395af0fcc2dafc5d10556978040c7a175ea;hp=f24cbadcdf2a1d39a5848797a40476f7a50b9dfe;hpb=48222bcd2d8f5e3afeabf05719225b11737c6baa;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index f24cbad..01ae55c 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()
-      uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true))
+      uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
     }
   }
 }