X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=3639d9baebef5c5ad1e5541e62f1a9e679ae52aa;hb=c010a1557aba5e1f9dc004c1ad9ec2cb26eabcfd;hp=fd5bc35db4838105187197ef82622c31c948a2d1;hpb=535be3e9761218a864bb553d996296dc65ea1735;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index fd5bc35..3639d9b 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -14,8 +14,8 @@ trait PeripheryUART {
   this: TopNetwork {
     val uartConfigs: Seq[UARTConfig]
   } =>
-  val uartDevices = uartConfigs.zipWithIndex.map { case (c, i) =>
-    val uart = LazyModule(new UART(c) { override lazy val valName = Some(s"uart$i") } )
+  val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
+    val uart = LazyModule(new UART(c))
     uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := uart.intnode
     uart
@@ -32,7 +32,7 @@ trait PeripheryUARTModule {
     val outer: PeripheryUART
     val io: PeripheryUARTBundle
   } =>
-  (io.uarts zip outer.uartDevices).foreach { case (io, device) =>
+  (io.uarts zip outer.uart).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }