X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=5564fef60fd934473aabb779331411cb68188917;hb=2139ab0d98a72072d3ab6116ab55b9e90b26cabe;hp=d42850f88eca4388a571ac86e47743c69406beef;hpb=0a80d1987d35046858c36a4fa462410b54a126f0;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index d42850f..5564fef 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.uart
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
 import sifive.blocks.util.ShiftRegisterInit
@@ -12,9 +12,10 @@ import sifive.blocks.util.ShiftRegisterInit
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
 trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
-  val uartParams = p(PeripheryUARTKey)  
+  val uartParams = p(PeripheryUARTKey)
+  val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
   val uarts = uartParams map { params =>
-    val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+    val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit)))
     uart.node := pbus.toVariableWidthSlaves
     ibus.fromSync := uart.intnode
     uart