X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=d94d5180941502ff3e3bc0f872d248f582c973d0;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hp=3639d9baebef5c5ad1e5541e62f1a9e679ae52aa;hpb=a915e84a9ee5fc195051c518f946322037e7cdb5;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 3639d9b..d94d518 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -2,53 +2,54 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import rocketchip._
-
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 import sifive.blocks.util.ShiftRegisterInit
 
-trait PeripheryUART {
-  this: TopNetwork {
-    val uartConfigs: Seq[UARTConfig]
-  } =>
-  val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
-    val uart = LazyModule(new UART(c))
-    uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+case object PeripheryUARTKey extends Field[Seq[UARTParams]]
+
+trait HasPeripheryUART extends HasSystemNetworks {
+  val uartParams = p(PeripheryUARTKey)  
+  val uarts = uartParams map { params =>
+    val uart = LazyModule(new TLUART(peripheryBusBytes, params))
+    uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := uart.intnode
     uart
   }
 }
 
-trait PeripheryUARTBundle {
-  this: { val uartConfigs: Seq[UARTConfig] } =>
-  val uarts = Vec(uartConfigs.size, new UARTPortIO)
+trait HasPeripheryUARTBundle {
+  val uart: Vec[UARTPortIO]
+
+  def tieoffUARTs(dummy: Int = 1) {
+    uart.foreach { _.rxd := UInt(1) }
+  }
+
 }
 
-trait PeripheryUARTModule {
-  this: TopNetworkModule {
-    val outer: PeripheryUART
-    val io: PeripheryUARTBundle
-  } =>
-  (io.uarts zip outer.uart).foreach { case (io, device) =>
+trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
+  val outer: HasPeripheryUART
+  val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
+
+  (uart zip outer.uarts).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
 
-class UARTPinsIO extends Bundle {
-  val rxd = new GPIOPin
-  val txd = new GPIOPin
-}
+class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
+  val rxd = pingen()
+  val txd = pingen()
 
-class UARTGPIOPort(syncStages: Int = 0) extends Module {
-  val io = new Bundle{
-    val uart = new UARTPortIO().flip()
-    val pins = new UARTPinsIO
+  def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+    withClockAndReset(clock, reset) {
+      txd.outputPin(uart.txd)
+      val rxd_t = rxd.inputPin()
+      uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
+    }
   }
-
-  GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
-  val rxd = GPIOInputPinCtrl(io.pins.rxd)
-  io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
 }
+