X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIG.scala;h=07f5562688adbe27501a12ed61adbb34c6ce7ee9;hb=360fe7e2a9c8f9982d1822baf6e56002a3705f9a;hp=7d864e4e8af77fb51f6b4b752fbe73bc67906cf6;hpb=a267a33b84f9419f23b0c8744018f39ae8127cc6;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 7d864e4..07f5562 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -24,7 +24,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
   val node = TLInputNode()
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
-      address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+      address = p(AXI4MemPortKey).address,
       resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,