X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIG.scala;h=7cdce954a9281f4f3d69666dcd3e77377c807667;hb=refs%2Fheads%2Fu500vc707devkit4GB-pre-shells;hp=5351cf0c2d2eef0a597a552d295c9a0d9deeecf6;hpb=5b78bd8451e6dd6a9eca059a85c52778e6d641bc;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 5351cf0..7cdce95 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -27,7 +27,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
   require (ranges.size == 1, "DDR range must be contiguous")
   val offset = ranges.head.base
   val depth = ranges.head.size
-  require((depth==0x40000000L) || (depth==0x100000000L)) //1GB or 4GB depth
+  require((depth<=0x100000000L),"vc707mig supports upto 4GB depth configuraton")
   
   val device = new MemoryDevice
   val node = TLInputNode()