X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIGPeriphery.scala;h=068f64cbd3a16987cbe6948202e762c0b7903039;hb=d973c659eb239d8bb1447ffe9a73df20cdd7bf04;hp=b52b37c0e699b99b2e1c453bb9f37e927582100f;hpb=7916ef5249c72a3a84c599d123760f4d716de58a;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index b52b37c..068f64c 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -2,25 +2,29 @@
 package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
-import diplomacy._
-import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
-import coreplex.BankedL2Config
+import freechips.rocketchip.coreplex.HasMemoryBus
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 
-trait PeripheryXilinxVC707MIG extends TopNetwork {
-  val module: PeripheryXilinxVC707MIGModule
+trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
+  val module: HasMemoryXilinxVC707MIGModuleImp
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
-  require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
-  val mem = Seq(xilinxvc707mig.node)
+
+  require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
+  xilinxvc707mig.node := memBuses.head.toDRAMController
 }
 
-trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
-  val xilinxvc707mig = new XilinxVC707MIGIO
+trait HasMemoryXilinxVC707MIGBundle {
+  val xilinxvc707mig: XilinxVC707MIGIO
+  def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
+    pads <> xilinxvc707mig
+  }
 }
 
-trait PeripheryXilinxVC707MIGModule extends TopNetworkModule {
-  val outer: PeripheryXilinxVC707MIG
-  val io: PeripheryXilinxVC707MIGBundle
+trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
+    with HasMemoryXilinxVC707MIGBundle {
+  val outer: HasMemoryXilinxVC707MIG
+  val xilinxvc707mig = IO(new XilinxVC707MIGIO)
 
-  io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
+  xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
 }