X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIGPeriphery.scala;h=068f64cbd3a16987cbe6948202e762c0b7903039;hb=d973c659eb239d8bb1447ffe9a73df20cdd7bf04;hp=bf187ff1ef15834abab712ee7038b79a6987d91b;hpb=dacca7e7b127f5578373c8aa28195ae189d81e51;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index bf187ff..068f64c 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -2,27 +2,28 @@
 package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
-import diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
+import freechips.rocketchip.coreplex.HasMemoryBus
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 
-trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks {
-  val module: HasPeripheryXilinxVC707MIGModuleImp
+trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
+  val module: HasMemoryXilinxVC707MIGModuleImp
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
+
   require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
-  xilinxvc707mig.node := mem(0).node
+  xilinxvc707mig.node := memBuses.head.toDRAMController
 }
 
-trait HasPeripheryXilinxVC707MIGBundle {
+trait HasMemoryXilinxVC707MIGBundle {
   val xilinxvc707mig: XilinxVC707MIGIO
   def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
     pads <> xilinxvc707mig
   }
 }
 
-trait HasPeripheryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
-    with HasPeripheryXilinxVC707MIGBundle {
-  val outer: HasPeripheryXilinxVC707MIG
+trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
+    with HasMemoryXilinxVC707MIGBundle {
+  val outer: HasMemoryXilinxVC707MIG
   val xilinxvc707mig = IO(new XilinxVC707MIGIO)
 
   xilinxvc707mig <> outer.xilinxvc707mig.module.io.port