X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIGPeriphery.scala;h=540821ecc4b336e90ede107e73851cd088b2edce;hb=fb9dd313741196a062e6a0f6462cf3a2bce710a9;hp=bf187ff1ef15834abab712ee7038b79a6987d91b;hpb=66b2fd11bd1ec6a8a05c4929893c51c7570284fd;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index bf187ff..540821e 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -2,8 +2,8 @@
 package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
-import diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
 
 trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks {
   val module: HasPeripheryXilinxVC707MIGModuleImp