X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707pciex1%2FXilinxVC707PCIeX1Periphery.scala;h=c994856f5b1c3b2cbffa87105cbc369323472e1a;hb=0ed21ba46590a23434d7ee55fa47bda3e114b4cd;hp=4a64766dbbb719e23e12abb8f515ebf4ebc4f1d6;hpb=5b6760394d963b7d3f835c4c79ed73dd2bff2e6a;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index 4a64766..c994856 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -3,25 +3,35 @@ package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
 import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
-import uncore.tilelink2.TLWidthWidget
+import rocketchip.{
+  HasTopLevelNetworks,
+  HasTopLevelNetworksModule,
+  HasTopLevelNetworksBundle
+}
+import uncore.tilelink2._
 
-trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
+trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
 
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-  l2.node := xilinxvc707pcie.master
-  xilinxvc707pcie.slave   := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  intBus.intnode := xilinxvc707pcie.intnode
+  private val intXing = LazyModule(new IntXing)
+
+  fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
+  xilinxvc707pcie.slave   := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+  xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+  intBus.intnode := intXing.intnode
+  intXing.intnode := xilinxvc707pcie.intnode
 }
 
-trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
+trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
   val xilinxvc707pcie = new XilinxVC707PCIeX1IO
 }
 
-trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
-  val outer: PeripheryXilinxVC707PCIeX1
-  val io: PeripheryXilinxVC707PCIeX1Bundle
+trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
+  val outer: HasPeripheryXilinxVC707PCIeX1
+  val io: HasPeripheryXilinxVC707PCIeX1Bundle
 
   io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+
+  outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
+  outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
 }