X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fip%2Fxilinx%2Fvc707axi_to_pcie_x1%2Fvc707axi_to_pcie_x1.scala;h=7e732f8160e5dfa6823f71cd4442756ad1240792;hb=d973c659eb239d8bb1447ffe9a73df20cdd7bf04;hp=a7cf844c10116211fccf5b1347650a5a5a1d09d7;hpb=7916ef5249c72a3a84c599d123760f4d716de58a;p=sifive-blocks.git

diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index a7cf844..7e732f8 100644
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -2,10 +2,10 @@
 package sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1
 
 import Chisel._
-import config._
-import diplomacy._
-import uncore.axi4._
-import junctions._
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
 
 // IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
 // Black Box
@@ -167,27 +167,54 @@ class vc707axi_to_pcie_x1() extends BlackBox
 
 class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
 {
-  val slave = AXI4SlaveNode(AXI4SlavePortParameters(
+  val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) {
+    override def describe(resources: ResourceBindings): Description = {
+      val Description(name, mapping) = super.describe(resources)
+      val intc = "pcie_intc"
+      def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
+      def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x)
+      val extra = Map(
+        "#address-cells"     -> ofInt(3),
+        "#size-cells"        -> ofInt(2),
+        "#interrupt-cells"   -> ofInt(1),
+        "device_type"        -> Seq(ResourceString("pci")),
+        "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
+        "interrupt-map"      -> Seq(1, 2, 3, 4).flatMap(ofMap),
+        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, perms)) =>
+                                                               ResourceMapping(address, BigInt(0x02000000) << 64, perms) },
+        "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
+          "interrupt-controller" -> Nil,
+          "#address-cells"       -> ofInt(0),
+          "#interrupt-cells"     -> ofInt(1)))))
+      Description(name, mapping ++ extra)
+    }
+  }
+
+  val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address       = List(AddressSet(0x60000000L, 0x1fffffffL)),
+      resources     = Seq(Resource(device, "ranges")),
       executable    = true,
       supportsWrite = TransferSizes(1, 256),
-      supportsRead  = TransferSizes(1, 256),
-      interleavedId = Some(0))), // the Xilinx IP is friendly
-    beatBytes = 8))
+      supportsRead  = TransferSizes(1, 256))),
+    beatBytes = 8)))
 
-  val control = AXI4SlaveNode(AXI4SlavePortParameters(
+  val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
+      resources     = device.reg("control"),
       supportsWrite = TransferSizes(1, 4),
       supportsRead  = TransferSizes(1, 4),
-      interleavedId = Some(0))), // no read interleaving b/c AXI-lite
-    beatBytes = 4))
+      interleavedId = Some(0))), // AXI4-Lite never interleaves responses
+    beatBytes = 4)))
 
-  val master = AXI4MasterNode(AXI4MasterPortParameters(
+  val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
     masters = Seq(AXI4MasterParameters(
+      name    = "VC707 PCIe",
       id      = IdRange(0, 1),
-      aligned = false))))
+      aligned = false)))))
+
+  val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
 
   lazy val module = new LazyModuleImp(this) {
     // The master on the control port must be AXI-lite
@@ -204,7 +231,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
       val control_in = control.bundleIn
       val master_out = master.bundleOut
       val REFCLK = Bool(INPUT)
-      val interrupt_out = Bool(OUTPUT)
+      val interrupt_out = intnode.bundleOut
     }
 
     val blackbox = Module(new vc707axi_to_pcie_x1)
@@ -222,7 +249,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
     io.port.pci_exp_txn             := blackbox.io.pci_exp_txn
     blackbox.io.pci_exp_rxp         := io.port.pci_exp_rxp
     blackbox.io.pci_exp_rxn         := io.port.pci_exp_rxn
-    io.interrupt_out                := blackbox.io.interrupt_out
+    io.interrupt_out(0)(0)          := blackbox.io.interrupt_out
     blackbox.io.REFCLK              := io.REFCLK
 
     //s