X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fip%2Fxilinx%2Fvc707mig%2Fvc707mig.scala;h=1e01748b531eac309e5f3087149ca1fee2619587;hb=d973c659eb239d8bb1447ffe9a73df20cdd7bf04;hp=923956b450e5d9d5987c2262d3dd5d5da1c1a916;hpb=7916ef5249c72a3a84c599d123760f4d716de58a;p=sifive-blocks.git

diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
index 923956b..1e01748 100644
--- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
@@ -2,15 +2,13 @@
 package sifive.blocks.ip.xilinx.vc707mig
 
 import Chisel._
-import config._
-import junctions._
+import chisel3.experimental.{Analog,attach}
+import freechips.rocketchip.config._
 
 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
 // Black Box
-// Signals named _exactly_ as per MIG generated verilog
 
-trait VC707MIGUnidirectionalIODDR extends Bundle {
-  //outputs
+trait VC707MIGIODDR extends Bundle {
   val ddr3_addr             = Bits(OUTPUT,14)
   val ddr3_ba               = Bits(OUTPUT,3)
   val ddr3_ras_n            = Bool(OUTPUT)
@@ -23,14 +21,17 @@ trait VC707MIGUnidirectionalIODDR extends Bundle {
   val ddr3_cs_n             = Bits(OUTPUT,1)
   val ddr3_dm               = Bits(OUTPUT,8)
   val ddr3_odt              = Bits(OUTPUT,1)
+
+  val ddr3_dq               = Analog(64.W)
+  val ddr3_dqs_n            = Analog(8.W)
+  val ddr3_dqs_p            = Analog(8.W)
 }
 
 //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
-trait VC707MIGUnidirectionalIOClocksReset extends Bundle {
+trait VC707MIGIOClocksReset extends Bundle {
   //inputs
-  //differential system clocks
-  val sys_clk_n             = Bool(INPUT)
-  val sys_clk_p             = Bool(INPUT)
+  //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
+  val sys_clk_i             = Bool(INPUT)
   //user interface signals
   val ui_clk                = Clock(OUTPUT)
   val ui_clk_sync_rst       = Bool(OUTPUT)
@@ -45,14 +46,8 @@ trait VC707MIGUnidirectionalIOClocksReset extends Bundle {
 //turn off linter: blackbox name must match verilog module 
 class vc707mig(implicit val p:Parameters) extends BlackBox
 {
-  val io = new Bundle with VC707MIGUnidirectionalIODDR
-                      with VC707MIGUnidirectionalIOClocksReset {
-    // bidirectional signals on blackbox interface
-    // defined here as an output so "__inout" signal name does not have to be used
-    // verilog does not check the
-    val ddr3_dq               = Bits(OUTPUT,64)
-    val ddr3_dqs_n            = Bits(OUTPUT,8)
-    val ddr3_dqs_p            = Bits(OUTPUT,8)
+  val io = new Bundle with VC707MIGIODDR
+                      with VC707MIGIOClocksReset {
     // User interface signals
     val app_sr_req            = Bool(INPUT)
     val app_ref_req           = Bool(INPUT)