X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Futil%2FRegMapFIFO.scala;h=698d8587aafe0cdee2dd6e5179695775db3cb211;hb=refs%2Fheads%2Ffreechips-packages;hp=3e4548242d1b63a0ebde1016d00d68c554a67925;hpb=66b2fd11bd1ec6a8a05c4929893c51c7570284fd;p=sifive-blocks.git

diff --git a/src/main/scala/util/RegMapFIFO.scala b/src/main/scala/util/RegMapFIFO.scala
index 3e45482..698d858 100644
--- a/src/main/scala/util/RegMapFIFO.scala
+++ b/src/main/scala/util/RegMapFIFO.scala
@@ -2,7 +2,7 @@
 package sifive.blocks.util
 
 import Chisel._
-import regmapper._
+import freechips.rocketchip.regmapper._
 
 // MSB indicates full status
 object NonBlockingEnqueue {