X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Futil%2FResetCatchAndSync.scala;h=6b483e53a2cce3dde7691545f56213684a0399c3;hb=fb9dd313741196a062e6a0f6462cf3a2bce710a9;hp=cc35686cc249a5d019422c64cb1b40a1a17cb33e;hpb=66b2fd11bd1ec6a8a05c4929893c51c7570284fd;p=sifive-blocks.git

diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala
index cc35686..6b483e5 100644
--- a/src/main/scala/util/ResetCatchAndSync.scala
+++ b/src/main/scala/util/ResetCatchAndSync.scala
@@ -2,7 +2,7 @@
 package sifive.blocks.util
 
 import Chisel._
-import util.AsyncResetRegVec
+import freechips.rocketchip.util.AsyncResetRegVec
 
 /** Reset: asynchronous assert,
   *  synchronous de-assert