X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Futil%2FTimer.scala;h=35e4a8341b8b3cc314a55870f3ad12d5118eca1e;hb=39287b92159e7f7a25635dfe7cc5cb7dc01488bc;hp=c46d2bef07ff68f6c677175be6f2b2b94ff07a5e;hpb=3e47ed6b335bc84d6469cf4c84eb1ccf5a0353cc;p=sifive-blocks.git

diff --git a/src/main/scala/util/Timer.scala b/src/main/scala/util/Timer.scala
index c46d2be..35e4a83 100644
--- a/src/main/scala/util/Timer.scala
+++ b/src/main/scala/util/Timer.scala
@@ -6,12 +6,10 @@ import Chisel.ImplicitConversions._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.util.WideCounter
 
-class SlaveRegIF(w: Int) extends Bundle {
+class SlaveRegIF(private val w: Int) extends Bundle {
   val write = Valid(UInt(width = w)).flip
   val read = UInt(OUTPUT, w)
 
-  override def cloneType: this.type = new SlaveRegIF(w).asInstanceOf[this.type]
-
   def toRegField(dummy: Int = 0): RegField = {
     def writeFn(valid: Bool, data: UInt): Bool = {
       write.valid := valid