X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fperipherals%2Frgbttl%2Frgbttl_dummy.bsv;h=0a4a7d87a03448fa3fdf11fc4f92262c80fde54b;hb=4126714e1df84a5e5df18f46b5cc773522d4e02e;hp=3bdb054c05e070fa903e8b0d30bf191210e6add6;hpb=30a5cf0653b662a3539adefda7157a50c5275716;p=shakti-peripherals.git

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
index 3bdb054..0a4a7d8 100644
--- a/src/peripherals/rgbttl/rgbttl_dummy.bsv
+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -29,6 +29,7 @@ Details:
 --------------------------------------------------------------------------------------------------
 */
 package rgbttl_dummy;
+  `define RGBTTL_WIDTH 18
   `include "instance_defines.bsv"
   import ClockDiv::*;
   import ConcatReg::*;
@@ -36,29 +37,25 @@ package rgbttl_dummy;
   import BUtils ::*;
   import AXI4_Lite_Types::*;
 
-  interface Ifc_rgbttl_dummy#(numeric type buswidth);
+  interface Ifc_rgbttl_dummy;
 	  interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
     method  Bit#(1) de; 
     method  Bit#(1) ck;
     method  Bit#(1) vs;
     method  Bit#(1) hs;
-    method  Bit#(buswidth) data;
+    method  Bit#(`RGBTTL_WIDTH) data;
   endinterface
 
   (*synthesize*)
-  module mkrgbttl_dummy(Ifc_rgbttl_dummy#(numeric type buswidth));
+  module mkrgbttl_dummy(Ifc_rgbttl_dummy);
 	  	AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
                             s_xactor<-mkAXI4_Lite_Slave_Xactor();
-      let v_buswidth = valueOf(v_buswidth);
 
       Reg#(Bit#(1)) rg_de <- mkReg(0);
       Reg#(Bit#(1)) rg_ck <- mkReg(0);
       Reg#(Bit#(1)) rg_vs <- mkReg(0);
       Reg#(Bit#(1)) rg_hs <- mkReg(0);
-      Reg#(Bit#(v_buswidth)) rg_data;
-      for(Integer i = 0; i < v_no_of_ir_pins;i=i+1) begin
-        rg_data[i] <- mkReg(0);
-      end
+      Reg#(Bit#(`RGBTTL_WIDTH)) rg_data <- mkReg(0);
 
     method  de = rg_de; 
     method  ck = rg_ck;