X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fperipherals%2Frgbttl%2Frgbttl_dummy.bsv;h=a52d5e7db27f36ee367a652d6a0ea0c6dbe3284f;hb=dc05aa4b16acab300b4afa10daa529c41969d871;hp=4d3b66b63ee3adf9c2c64c36f306a16f302dc002;hpb=cc537c6a6770ae44f570d344d2f4acf47754ea7f;p=shakti-peripherals.git

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
index 4d3b66b..a52d5e7 100644
--- a/src/peripherals/rgbttl/rgbttl_dummy.bsv
+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -31,14 +31,13 @@ Details:
 package rgbttl_dummy;
   `define RGBTTL_WIDTH 18
   `include "instance_defines.bsv"
-  import ClockDiv::*;
-  import ConcatReg::*;
-  import Semi_FIFOF::*;
+  import GetPut::*;
   import BUtils ::*;
-  import AXI4_Lite_Types::*;
+  import AXI4_Types::*;
 
   interface Ifc_rgbttl_dummy;
-	  interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+	    interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+	    interface AXI4_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
       interface Get#(Bit#(1)) de;
       interface Get#(Bit#(1)) ck;
       interface Get#(Bit#(1)) vs;
@@ -48,8 +47,10 @@ package rgbttl_dummy;
 
   (*synthesize*)
   module mkrgbttl_dummy(Ifc_rgbttl_dummy);
-	  	AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
-                            s_xactor<-mkAXI4_Lite_Slave_Xactor();
+	  	AXI4_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+                            s_xactor<-mkAXI4_Slave_Xactor();
+	  	AXI4_Master_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+                            m_xactor<-mkAXI4_Master_Xactor();
 
       Reg#(Bit#(1)) rg_de <- mkReg(0);
       Reg#(Bit#(1)) rg_ck <- mkReg(0);
@@ -81,12 +82,13 @@ package rgbttl_dummy;
         endmethod
       endinterface;
 
-      interface data = interface Get
+      interface data_out = interface Get
         method ActionValue#(Bit#(`RGBTTL_WIDTH)) get;
-          return data_out;
+          return rg_data;
         endmethod
       endinterface;
 
       interface slave=s_xactor.axi_side;
+      interface master=m_xactor.axi_side;
   endmodule
 endpackage