X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fscoreboard%2Ffu_fu_matrix.py;h=ee715bdbf292d92495d4dac653aa1f80292b6fcc;hb=a67982ac0531707ace79e27a89132538bbff41f2;hp=5d8b2cb21d7db509fd6633b9f8b6cfcfc1c52aad;hpb=f9f502cad611e7dd9fa28abec41f14b59469501d;p=soc.git

diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py
index 5d8b2cb2..ee715bdb 100644
--- a/src/scoreboard/fu_fu_matrix.py
+++ b/src/scoreboard/fu_fu_matrix.py
@@ -37,11 +37,10 @@ class FUFUDepMatrix(Elaboratable):
         # ---
         # matrix of dependency cells
         # ---
-        dm = Array(Array(FUDependenceCell() for r in range(self.n_fu_row)) \
+        dm = Array(FUDependenceCell(self.n_fu_row) \
                                             for f in range(self.n_fu_col))
         for x in range(self.n_fu_col):
-            for y in range(self.n_fu_row):
-                setattr(m.submodules, "dm_fx%d_fy%d" % (x, y), dm[x][y])
+                setattr(m.submodules, "dm%d" % x, dm[x])
 
         # ---
         # array of Function Unit Readable/Writable: row-length, horizontal
@@ -73,23 +72,24 @@ class FUFUDepMatrix(Elaboratable):
             rd_wait_o = []
             wr_wait_o = []
             for x in range(self.n_fu_col):
-                dc = dm[x][y]
+                dc = dm[x]
                 # accumulate cell outputs rd/wr-pending
-                rd_wait_o.append(dc.rd_wait_o)
-                wr_wait_o.append(dc.wr_wait_o)
+                rd_wait_o.append(dc.rd_wait_o[y])
+                wr_wait_o.append(dc.wr_wait_o[y])
             # connect cell reg-select outputs to Reg Vector In
             m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_wait_o)),
                          fu.wr_pend_i.eq(Cat(*wr_wait_o)),
                         ]
+
         # ---
         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
         # ---
         for x in range(self.n_fu_col):
+            dc = dm[x]
             issue_i = []
             for y in range(self.n_fu_row):
-                dc = dm[x][y]
                 # accumulate cell inputs issue
-                issue_i.append(dc.issue_i)
+                issue_i.append(dc.issue_i[y])
             # wire up inputs from module to row cell inputs (Cat is gooood)
             m.d.comb += Cat(*issue_i).eq(self.issue_i)
 
@@ -101,17 +101,18 @@ class FUFUDepMatrix(Elaboratable):
             go_wr_i = []
             go_die_i = []
             for x in range(self.n_fu_col):
-                dc = dm[x][y]
+                dc = dm[x]
                 # accumulate cell go_rd/go_wr
-                go_rd_i.append(dc.go_rd_i)
-                go_wr_i.append(dc.go_wr_i)
-                go_die_i.append(dc.go_die_i)
+                go_rd_i.append(dc.go_rd_i[y])
+                go_wr_i.append(dc.go_wr_i[y])
+                go_die_i.append(dc.go_die_i[y])
             # wire up inputs from module to row cell inputs (Cat is gooood)
             m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
                          Cat(*go_wr_i).eq(self.go_wr_i),
                          Cat(*go_die_i).eq(self.go_die_i),
                         ]
 
+
         # ---
         # connect Matrix pending
         # ---
@@ -119,16 +120,16 @@ class FUFUDepMatrix(Elaboratable):
             rd_pend_i = []
             wr_pend_i = []
             for x in range(self.n_fu_col):
+                dc = dm[x]
                 if x == y: # ignore hazards on the diagonal: self-against-self
                     dummyrd = Signal(reset_less=True)
                     dummywr = Signal(reset_less=True)
                     rd_pend_i.append(dummyrd)
                     wr_pend_i.append(dummywr)
                     continue
-                dc = dm[x][y]
                 # accumulate cell rd_pend/wr_pend/go_rd/go_wr
-                rd_pend_i.append(dc.rd_pend_i)
-                wr_pend_i.append(dc.wr_pend_i)
+                rd_pend_i.append(dc.rd_pend_i[y])
+                wr_pend_i.append(dc.wr_pend_i[y])
             # wire up inputs from module to row cell inputs (Cat is gooood)
             m.d.comb += [Cat(*rd_pend_i).eq(self.rd_pend_i),
                          Cat(*wr_pend_i).eq(self.wr_pend_i),