X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fbus%2Fopencores_ethmac.py;h=5720c1ce65ce4cc06b920f30e5c800c1cfa5b3ca;hb=d982e1ef558d7d3d4b26b4108f1e01d59bf0663d;hp=3078fa67dc0aa07c99f42af24965d45040336204;hpb=a07858e1ba92c5006ede0ec1aff4875f736a8810;p=soc.git

diff --git a/src/soc/bus/opencores_ethmac.py b/src/soc/bus/opencores_ethmac.py
index 3078fa67..5720c1ce 100644
--- a/src/soc/bus/opencores_ethmac.py
+++ b/src/soc/bus/opencores_ethmac.py
@@ -111,6 +111,7 @@ class EthMAC(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
+        idx = self.idx
 
         # Calculate arbiter bus address
         wb_master_bus_adr = Signal(32)
@@ -119,7 +120,6 @@ class EthMAC(Elaboratable):
 
         # create definition of external verilog EthMAC code here, so that
         # nmigen understands I/O directions (defined by i_ and o_ prefixes)
-        idx = self.idx
         ethmac = Instance("eth_top",
                             # Clock/reset (use DomainRenamer if needed)
                             i_wb_clk_i=ClockSignal(),