X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fbus%2Ftercel.py;h=328bf661d374589f7fefc859467b55e7e9597e9f;hb=620567c020d80a0585ffad37eb35508c59e47f8b;hp=102218236a5faa2830ff8e83395798fc741b7aa2;hpb=e71dc3c11a1085aa609833a4a3c2eecd2f18876e;p=soc.git

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index 10221823..328bf661 100644
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -50,7 +50,8 @@ class Tercel(Elaboratable):
 
         # set up the wishbone busses
         if features is None:
-            features = frozenset({'err'})
+            #features = frozenset({'err'}) # sigh
+            features = frozenset()
         if bus is None:
             bus = Interface(addr_width=spi_region_addr_width,
                             data_width=data_width,
@@ -138,7 +139,7 @@ class Tercel(Elaboratable):
                             i_wishbone_stb=bus.stb,
                             i_wishbone_cyc=bus.cyc,
                             o_wishbone_ack=bus.ack,
-                            o_wishbone_err=bus.err,
+                            #o_wishbone_err=bus.err,
 
                             # Configuration region Wishbone bus signals
                             i_cfg_wishbone_adr=cfg_bus.adr,
@@ -149,7 +150,7 @@ class Tercel(Elaboratable):
                             i_cfg_wishbone_stb=cfg_bus.stb,
                             i_cfg_wishbone_cyc=cfg_bus.cyc,
                             o_cfg_wishbone_ack=cfg_bus.ack,
-                            o_cfg_wishbone_err=cfg_bus.err,
+                            #o_cfg_wishbone_err=cfg_bus.err,
 
                             # QSPI signals
                             o_spi_d_out=self.dq_out,