X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fbus%2Ftercel.py;h=934fda20e584e83b18f765766bc9907a253d7f59;hb=9e4e5fb690bf8a893c17f5f02ffbb6728f720eb8;hp=1e204b5a582516dabfd7a41b8544b2cc8bbef029;hpb=955f5d408051d75f20355b6c5f4fb98d64d8c263;p=soc.git

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index 1e204b5a..934fda20 100644
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -45,7 +45,7 @@ class Tercel(Elaboratable):
         # TODO, sort this out.
         assert clk_freq is not None
         clk_freq = round(clk_freq)
-        self.clk_freq = Const(clk_freq, clk_freq.bit_length())
+        self.clk_freq = Const(clk_freq, 32) #clk_freq.bit_length())
 
         # set up the wishbone busses
         if features is None: