X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdebug%2Fdmi.py;h=03bd8dc8eabcde75a191147a666ad9086b120ac5;hb=265c6ea8ac681d82d4d12f26389d26beb5060f9b;hp=e83491824322888050cd853596bf2ae335467553;hpb=c916a9d059b3aa772f06c2622854da093db8a13b;p=soc.git

diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py
index e8349182..03bd8dc8 100644
--- a/src/soc/debug/dmi.py
+++ b/src/soc/debug/dmi.py
@@ -292,10 +292,13 @@ class CoreDebug(Elaboratable):
         comb += d_fast.addr.eq(fast_index)
 
         # Core control signals generated by the debug module
-        comb += self.core_stop_o.eq((stopping & ~do_step) | self.terminate_i)
+        # Note: make stop and terminated synchronous, to help with timing
+        # however this *may* interfere with some of the DMI-based unit tests
+        # so has to be kept an eye on
+        sync += self.core_stop_o.eq((stopping & ~do_step) | self.terminate_i)
+        sync += self.terminated_o.eq(terminated | self.terminate_i)
         comb += self.core_rst_o.eq(do_reset)
         comb += self.icache_rst_o.eq(do_icreset)
-        comb += self.terminated_o.eq(terminated | self.terminate_i)
 
         # Logging RAM (none)