X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fisa%2Fcaller.py;h=39d99d5e4fbe4d6fec12999e48e0514e6835bdfe;hb=5d496a6b50ec3b9e00586e777651c60a1921688d;hp=2199d731348e0453f744e64c65b9492ceda2e047;hpb=b6fd6ec34ccea3928f96a7c193f9d041cc374efd;p=soc.git

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 2199d731..39d99d5e 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -129,15 +129,17 @@ class ISACaller:
         # from spec
         # then "yield" fields only from op_fields rather than hard-coded
         # list, here.
-        for name in ['SI', 'UI', 'D', 'BD']:
-            signal = getattr(self.decoder, name)
-            val = yield signal
-            self.namespace[name] = SelectableInt(val, bits=signal.width)
+        fields = self.decoder.sigforms[formname]
+        for name in fields._fields:
+            if name not in ["RA", "RB", "RT"]:
+                sig = getattr(fields, name)
+                val = yield sig
+                self.namespace[name] = SelectableInt(val, sig.width)
 
     def call(self, name):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
-        fn, read_regs, uninit_regs, write_regs, op_fields, asmregs, form \
+        fn, read_regs, uninit_regs, write_regs, op_fields, form, asmregs \
             = self.instrs[name]
         yield from self.prep_namespace(form, op_fields)