X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fisa%2Fcaller.py;h=39d99d5e4fbe4d6fec12999e48e0514e6835bdfe;hb=5d496a6b50ec3b9e00586e777651c60a1921688d;hp=7bd2ca2180b901f88f684e37f51d2841b4f0ee10;hpb=a7461016183d1ca9e350b70e6bb22d557263972d;p=soc.git diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 7bd2ca21..39d99d5e 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -1,26 +1,72 @@ from functools import wraps +from soc.decoder.orderedset import OrderedSet from soc.decoder.selectable_int import SelectableInt, selectconcat +import math +def create_args(reglist, extra=None): + args = OrderedSet() + for reg in reglist: + args.add(reg) + args = list(args) + if extra: + args = [extra] + args + return args class Mem: - def __init__(self): - self.mem = [] - for i in range(128): - self.mem.append(i) + def __init__(self, bytes_per_word=8): + self.mem = {} + self.bytes_per_word = bytes_per_word + self.word_log2 = math.ceil(math.log2(bytes_per_word)) + + def _get_shifter_mask(self, width, remainder): + shifter = ((self.bytes_per_word - width) - remainder) * \ + 8 # bits per byte + mask = (1 << (width * 8)) - 1 + return shifter, mask + + # TODO: Implement ld/st of lesser width + def ld(self, address, width=8): + remainder = address & (self.bytes_per_word - 1) + address = address >> self.word_log2 + assert remainder & (width - 1) == 0, "Unaligned access unsupported!" + if address in self.mem: + val = self.mem[address] + else: + val = 0 + + if width != self.bytes_per_word: + shifter, mask = self._get_shifter_mask(width, remainder) + val = val & (mask << shifter) + val >>= shifter + print("Read {:x} from addr {:x}".format(val, address)) + return val + + def st(self, address, value, width=8): + remainder = address & (self.bytes_per_word - 1) + address = address >> self.word_log2 + assert remainder & (width - 1) == 0, "Unaligned access unsupported!" + print("Writing {:x} to addr {:x}".format(value, address)) + if width != self.bytes_per_word: + if address in self.mem: + val = self.mem[address] + else: + val = 0 + shifter, mask = self._get_shifter_mask(width, remainder) + val &= ~(mask << shifter) + val |= value << shifter + self.mem[address] = val + else: + self.mem[address] = value def __call__(self, addr, sz): - res = [] - for s in range(sz): # TODO: big/little-end - res.append(SelectableInt(self.mem[addr.value + s], 8)) - print ("memread", addr, sz, res) - return selectconcat(*res) + val = self.ld(addr.value, sz) + print ("memread", addr, sz, val) + return SelectableInt(val, sz*8) def memassign(self, addr, sz, val): print ("memassign", addr, sz, val) - for s in range(sz): - byte = (val.value) >> (s*8) & 0xff # TODO: big/little-end - self.mem[addr.value + s] = byte + self.st(addr.value, val.value, sz) class GPR(dict): @@ -53,9 +99,17 @@ class GPR(dict): rnum = self._get_regnum(attr) return self.regfile[rnum] + def dump(self): + for i in range(0, len(self), 8): + s = [] + for j in range(8): + s.append("%08x" % self[i+j].value) + s = ' '.join(s) + print("reg", "%2d" % i, s) + class ISACaller: - # decoder2 - an instance of power_decoder2 + # decoder2 - an instance of power_decoder2 # regfile - a list of initial values for the registers def __init__(self, decoder2, regfile): self.gpr = GPR(decoder2, regfile) @@ -63,13 +117,57 @@ class ISACaller: self.namespace = {'GPR': self.gpr, 'MEM': self.mem, 'memassign': self.memassign - } + } + self.decoder = decoder2 def memassign(self, ea, sz, val): self.mem.memassign(ea, sz, val) - -def inject(context): + def prep_namespace(self, formname, op_fields): + # TODO: get field names from form in decoder*1* (not decoder2) + # decoder2 is hand-created, and decoder1.sigform is auto-generated + # from spec + # then "yield" fields only from op_fields rather than hard-coded + # list, here. + fields = self.decoder.sigforms[formname] + for name in fields._fields: + if name not in ["RA", "RB", "RT"]: + sig = getattr(fields, name) + val = yield sig + self.namespace[name] = SelectableInt(val, sig.width) + + def call(self, name): + # TODO, asmregs is from the spec, e.g. add RT,RA,RB + # see http://bugs.libre-riscv.org/show_bug.cgi?id=282 + fn, read_regs, uninit_regs, write_regs, op_fields, form, asmregs \ + = self.instrs[name] + yield from self.prep_namespace(form, op_fields) + + input_names = create_args(read_regs | uninit_regs) + print(input_names) + + inputs = [] + for name in input_names: + regnum = yield getattr(self.decoder, name) + regname = "_" + name + self.namespace[regname] = regnum + print('reading reg %d' % regnum) + inputs.append(self.gpr(regnum)) + print(inputs) + results = fn(self, *inputs) + print(results) + + if write_regs: + output_names = create_args(write_regs) + for name, output in zip(output_names, results): + regnum = yield getattr(self.decoder, name) + print('writing reg %d' % regnum) + if output.bits > 64: + output = SelectableInt(output.value, 64) + self.gpr[regnum] = output + + +def inject(): """ Decorator factory. """ def variable_injector(func): @wraps(func) @@ -79,6 +177,7 @@ def inject(context): except AttributeError: func_globals = func.func_globals # Earlier versions. + context = args[0].namespace saved_values = func_globals.copy() # Shallow copy of dict. func_globals.update(context) @@ -94,20 +193,3 @@ def inject(context): return variable_injector -if __name__ == '__main__': - d = {'1': 1} - namespace = {'a': 5, 'b': 3, 'd': d} - - @inject(namespace) - def test(): - print (globals()) - print('a:', a) - print('b:', b) - print('d1:', d['1']) - d[2] = 5 - - return locals() - - test() - - print (namespace)