X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fpower_enums.py;h=0d610df7771500fb54d4da8df569ab162c196873;hb=HEAD;hp=b480eabaf5550d74739aeb0aea0da2a26a77deae;hpb=e014f0dec6a5ed4f5ed8947316a5f5d6870eaf58;p=soc.git

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index b480eaba..0d610df7 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -1,225 +1,5 @@
-from enum import Enum, unique
-import csv
-import os
-import requests
-from os.path import dirname, join
+# moved to openpower-isa
+# https://git.libre-soc.org/?p=openpower-isa.git;a=summary
+# wildcard imports here ONLY to support migration
 
-def find_wiki_file(name):
-    filedir = os.path.dirname(os.path.abspath(__file__))
-    basedir = dirname(dirname(dirname(filedir)))
-    tabledir = join(basedir, 'libreriscv')
-    tabledir = join(tabledir, 'openpower')
-    tabledir = join(tabledir, 'isatables')
-
-    file_path = join(tabledir, name)
-    return file_path
-
-
-def get_csv(name):
-    file_path = find_wiki_file(name)
-    with open(file_path, 'r') as csvfile:
-        reader = csv.DictReader(csvfile)
-        return list(reader)
-
-
-# names of the fields in the tables that don't correspond to an enum
-single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
-                    'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
-                    'sgn', 'lk', 'sgl pipe']
-
-# default values for fields in the table
-default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
-                  'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
-                  'ldst len': 'NONE',
-                  'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
-
-
-def get_signal_name(name):
-    if name[0].isdigit():
-        name = "is_" + name
-    return name.lower().replace(' ', '_')
-
-
-@unique
-class Function(Enum):
-    NONE = 0
-    ALU = 1
-    LDST = 2
-
-
-@unique
-class Form(Enum):
-    NONE = 0
-    I = 1
-    B = 2
-    SC = 3
-    D = 4
-    DS = 5
-    DQ = 6
-    DX = 7
-    X = 8
-    XL = 9
-    XFX = 10
-    XFL = 11
-    XX1 = 12
-    XX2 = 13
-    XX3 = 14
-    XX4 = 15
-    XS = 16
-    XO = 17
-    A = 18
-    M = 19
-    MD = 20
-    MDS = 21
-    VA = 22
-    VC = 23
-    VX = 24
-    EVX = 25
-    EVS = 26
-    Z22 = 27
-    Z23 = 28
-
-
-# Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
-@unique
-class InternalOp(Enum):
-    OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
-    OP_NOP = 1
-    OP_ADD = 2
-    OP_ADDPCIS = 3
-    OP_AND = 4
-    OP_ATTN = 5
-    OP_B = 6
-    OP_BC = 7
-    OP_BCREG = 8
-    OP_BPERM = 9
-    OP_CMP = 10
-    OP_CMPB = 11
-    OP_CMPEQB = 12
-    OP_CMPRB = 13
-    OP_CNTZ = 14
-    OP_CRAND = 15
-    OP_CRANDC = 16
-    OP_CREQV = 17
-    OP_CRNAND = 18
-    OP_CRNOR = 19
-    OP_CROR = 20
-    OP_CRORC = 21
-    OP_CRXOR = 22
-    OP_DARN = 23
-    OP_DCBF = 24
-    OP_DCBST = 25
-    OP_DCBT = 26
-    OP_DCBTST = 27
-    OP_DCBZ = 28
-    OP_DIV = 29
-    OP_DIVE = 30
-    OP_EXTS = 31
-    OP_EXTSWSLI = 32
-    OP_ICBI = 33
-    OP_ICBT = 34
-    OP_ISEL = 35
-    OP_ISYNC = 36
-    OP_LOAD = 37
-    OP_STORE = 38
-    OP_MADDHD = 39
-    OP_MADDHDU = 40
-    OP_MADDLD = 41
-    OP_MCRF = 42
-    OP_MCRXR = 43
-    OP_MCRXRX = 44
-    OP_MFCR = 45
-    OP_MFSPR = 46
-    OP_MOD = 47
-    OP_MTCRF = 48
-    OP_MTSPR = 49
-    OP_MUL_L64 = 50
-    OP_MUL_H64 = 51
-    OP_MUL_H32 = 52
-    OP_OR = 53
-    OP_POPCNT = 54
-    OP_PRTY = 55
-    OP_RLC = 56
-    OP_RLCL = 57
-    OP_RLCR = 58
-    OP_SETB = 59
-    OP_SHL = 60
-    OP_SHR = 61
-    OP_SYNC = 62
-    OP_TD = 63
-    OP_TDI = 64
-    OP_TW = 65
-    OP_TWI = 66
-    OP_XOR = 67
-    OP_SIM_CONFIG = 68
-
-
-@unique
-class In1Sel(Enum):
-    NONE = 0
-    RA = 1
-    RA_OR_ZERO = 2
-    SPR = 3
-
-
-@unique
-class In2Sel(Enum):
-    NONE = 0
-    RB = 1
-    CONST_UI = 2
-    CONST_SI = 3
-    CONST_UI_HI = 4
-    CONST_SI_HI = 5
-    CONST_LI = 6
-    CONST_BD = 7
-    CONST_DS = 8
-    CONST_M1 = 9
-    CONST_SH = 10
-    CONST_SH32 = 11
-    SPR = 12
-
-
-@unique
-class In3Sel(Enum):
-    NONE = 0
-    RS = 1
-
-
-@unique
-class OutSel(Enum):
-    NONE = 0
-    RT = 1
-    RA = 2
-    SPR = 3
-
-
-@unique
-class LdstLen(Enum):
-    NONE = 0
-    is1B = 1
-    is2B = 2
-    is4B = 3
-    is8B = 4
-
-
-@unique
-class RC(Enum):
-    NONE = 0
-    ONE = 1
-    RC = 2
-
-
-@unique
-class CryIn(Enum):
-    ZERO = 0
-    ONE = 1
-    CA = 2
-
-
-# SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
-# http://libre-riscv.org/openpower/isatables/sprs.csv
-# http://bugs.libre-riscv.org/show_bug.cgi?id=261
-
-spr_csv = get_csv("sprs.csv")
-fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
-SPR = Enum('SPR', fields)
+from openpower.decoder.power_enums import *