X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Fcache_ram.py;h=784b9a8151fac8578dca8a1b95404480d9e509f3;hb=348b371b5084f0eda168b31aefb9088a2c24a1ae;hp=a79b68723a566e8bfcc88c97033949c8453ad3ec;hpb=fdd55337edc5856dc5ae0c35cd6ad28151bfc441;p=soc.git

diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py
index a79b6872..784b9a81 100644
--- a/src/soc/experiment/cache_ram.py
+++ b/src/soc/experiment/cache_ram.py
@@ -32,7 +32,8 @@ class CacheRam(Elaboratable):
         # set up the Cache RAM Memory and create one read and one write port
         # the read port is *not* transparent (does not pass write-thru-read)
         #attribute ram_style of ram : signal is "block";
-        ram = Memory(depth=SIZE, width=WIDTH)
+        ram = Memory(depth=SIZE, width=WIDTH,
+                     attrs={'syn_ramstyle': "block_ram"})
         m.submodules.rdport = rdport = ram.read_port(transparent=False)
         m.submodules.wrport = wrport = ram.write_port(granularity=8)