X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Fcompalu_multi.py;h=3d1f7249af461fea77452dce19cdc57267330d13;hb=faf46e0e0efd0c43e2d991ea4eaaca30fdd30701;hp=d33be619d01ddac18539a7873da644ae7fa190c8;hpb=d0b50601e54bc4eb73c9b78364baf522087402e8;p=soc.git

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index d33be619..3d1f7249 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -258,7 +258,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         # src operand latch (not using go_wr_i) ANDed with rdmask
         rdmaskn = Signal(self.n_src)
         latchregister(m, self.rdmaskn, rdmaskn, self.issue_i, name="rdmask_l")
-        m.d.comb += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~rdmaskn)
+        m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~rdmaskn)
         m.d.sync += src_l.r.eq(reset_r)
 
         # dest operand latch (not using issue_i)