X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Fformal%2Fproof_compalu_multi.py;h=f8d6fb0fd85f3a3fcf8014c1e84e4c57d19c014f;hb=003791ed6230b3a45278cdcb7781526911688c9a;hp=fd3a50f0e8c469e9cc5bfed483937294c825f60c;hpb=e33da1093516e48b93bd7a0807658e5cd9f90d1c;p=soc.git

diff --git a/src/soc/experiment/formal/proof_compalu_multi.py b/src/soc/experiment/formal/proof_compalu_multi.py
index fd3a50f0..f8d6fb0f 100644
--- a/src/soc/experiment/formal/proof_compalu_multi.py
+++ b/src/soc/experiment/formal/proof_compalu_multi.py
@@ -101,6 +101,8 @@ class CompALUMultiTestCase(FHDLTestCase):
         # Instantiate "random" ALU
         alu = ALU()
         m.submodules.dut = dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
+        # TODO Test shadow / die
+        m.d.comb += [dut.shadown_i.eq(1), dut.go_die_i.eq(0)]
         # Transaction counters
         do_issue = Signal()
         m.d.comb += do_issue.eq(dut.issue_i & ~dut.busy_o)