X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Ftest%2Ftest_l0_cache_buffer2.py;h=c331a7b5e5958238a78d5c28f5fdcab873aa351d;hb=ff6742035f643135729e19c531f0aa9d86934972;hp=066cf431e62577e7d9524c421dcab2153a9f64f8;hpb=442546d5bffafb8571f50b1a4dc48e83ace1ce47;p=soc.git

diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py
index 066cf431..c331a7b5 100644
--- a/src/soc/experiment/test/test_l0_cache_buffer2.py
+++ b/src/soc/experiment/test/test_l0_cache_buffer2.py
@@ -25,10 +25,10 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
         super().__init__(regwid, addrwid)
         self.ldst = LDSTSplitter(32, 48, 4)
 
-    def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz):
+    def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz, is_nc):
         m.d.comb += self.ldst.addr_i.eq(addr)
 
-    def set_rd_addr(self, m, addr, mask, misalign, msr):
+    def set_rd_addr(self, m, addr, mask, misalign, msr, is_nc):
         m.d.comb += self.ldst.addr_i.eq(addr)
 
     def set_wr_data(self, m, data, wen):