X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fregspec.py;h=f5971aadff87b2cad67b9d6610ee929f2081f11f;hb=fb3528750f912a762984a79654cce6601c52a994;hp=6804c593971fab5adcce20ddccaf797439a65e86;hpb=32b2120c0bd42fcf2c15e7f93df7efb76bb8b835;p=soc.git

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 6804c593..f5971aad 100644
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -39,6 +39,7 @@ def get_regspec_bitwidth(regspec, srcdest, idx):
 class RegSpec:
     def __init__(self, rwid, n_src=None, n_dst=None, name=None):
         self._rwid = rwid
+        print ("RegSpec", rwid)
         if isinstance(rwid, int):
             # rwid: integer (covers all registers)
             self._n_src, self._n_dst = n_src, n_dst