X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fshift_rot%2Ftest%2Ftest_maskgen.py;h=8898224d5a089ff3039a69f8ea3543998cbee67d;hb=74c68266bb10e37f2bb118cb338f9e48cb036daa;hp=27a1d4c495526b22a92246aa20599c2c7d4a24a9;hpb=f5a7184a807b68d8e314d7fc74e91a01b4237600;p=soc.git

diff --git a/src/soc/fu/shift_rot/test/test_maskgen.py b/src/soc/fu/shift_rot/test/test_maskgen.py
index 27a1d4c4..8898224d 100644
--- a/src/soc/fu/shift_rot/test/test_maskgen.py
+++ b/src/soc/fu/shift_rot/test/test_maskgen.py
@@ -3,12 +3,13 @@ from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 from soc.fu.shift_rot.maskgen import MaskGen
-from openpower.decoder.helpers import MASK
+from openpower.decoder.helpers import ISACallerHelper
 import random
 import unittest
 
 class MaskGenTestCase(FHDLTestCase):
     def test_maskgen(self):
+        MASK = ISACallerHelper(64, FPSCR=None).MASK
         m = Module()
         comb = m.d.comb
         m.submodules.dut = dut = MaskGen(64)