X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fregfile%2Fregfile.py;h=2427a680a94ad5f7dac71b013579dba05bfea27c;hb=057b1428bcb8bfe8669650f3823c08f1ae7ab010;hp=07cee2dd6773eb0644da0f9b5216d4f0a1dde7f6;hpb=2b6da534d53396208ddb6b40fb8c13f4ad7d4058;p=soc.git

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index 07cee2dd..2427a680 100644
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -56,7 +56,8 @@ class Register(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        self.reg = reg = Signal(self.width, name="reg", reset=self.reset)
+        self.reg = reg = Signal(self.width, name="reg", reset=self.reset,
+                                attrs={'syn_ramstyle': "block_ram"})
 
         if self.synced:
             domain = m.d.sync
@@ -290,7 +291,9 @@ class RegFile(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         bsz = int(log(self.width) / log(2))
-        regs = Array(Signal(self.width, name="reg") for _ in range(self.depth))
+        regs = Array(Signal(self.width, name="reg",
+                            attrs={'syn_ramstyle': "block_ram"}) \
+                    for _ in range(self.depth))
 
         # read ports. has write-through detection (returns data written)
         for rp in self._rdports: