X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fregfile%2Fsram_wrapper.py;h=ce58793fbf5c50e9551e7cbac8f0cef577763bcd;hb=d6055d7579bdfb38db5fcc12916493f60a8828dd;hp=37fad02028d5856c17abc1fceb1c16b20221e130;hpb=332653c94f0e6369fa8d96087a7e392430a10daf;p=soc.git

diff --git a/src/soc/regfile/sram_wrapper.py b/src/soc/regfile/sram_wrapper.py
index 37fad020..ce58793f 100644
--- a/src/soc/regfile/sram_wrapper.py
+++ b/src/soc/regfile/sram_wrapper.py
@@ -40,18 +40,12 @@ class SinglePortSRAM(Elaboratable):
         self.addr_width = addr_width
         self.data_width = data_width
         self.we_width = we_width
-        self.d = Signal(data_width)
-        """ write data"""
-        self.q = Signal(data_width)
-        """read data"""
-        self.a = Signal(addr_width)
-        """ read/write address"""
-        self.we = Signal(we_width)
-        """write enable"""
-        self.dbg_a = Signal(addr_width)
-        """debug read port address"""
-        self.dbg_q = Signal(data_width)
-        """debug read port data"""
+        self.d = Signal(data_width); """ write data"""
+        self.q = Signal(data_width); """read data"""
+        self.a = Signal(addr_width); """ read/write address"""
+        self.we = Signal(we_width); """write enable"""
+        self.dbg_a = Signal(addr_width); """debug read port address"""
+        self.dbg_q = Signal(data_width); """debug read port data"""
 
     def elaborate(self, _):
         m = Module()
@@ -254,24 +248,15 @@ class PhasedDualPortRegfile(Elaboratable):
         self.we_width = we_width
         self.write_phase = write_phase
         self.transparent = transparent
-        self.wr_addr_i = Signal(addr_width)
-        """write port address"""
-        self.wr_data_i = Signal(data_width)
-        """write port data"""
-        self.wr_we_i = Signal(we_width)
-        """write port enable"""
-        self.rd_addr_i = Signal(addr_width)
-        """read port address"""
-        self.rd_data_o = Signal(data_width)
-        """read port data"""
-        self.phase = Signal()
-        """even/odd cycle indicator"""
-        self.dbg_a = Signal(addr_width)
-        """debug read port address"""
-        self.dbg_q1 = Signal(data_width)
-        """debug read port data (first memory)"""
-        self.dbg_q2 = Signal(data_width)
-        """debug read port data (second memory)"""
+        self.wr_addr_i = Signal(addr_width); """write port address"""
+        self.wr_data_i = Signal(data_width); """write port data"""
+        self.wr_we_i = Signal(we_width); """write port enable"""
+        self.rd_addr_i = Signal(addr_width); """read port address"""
+        self.rd_data_o = Signal(data_width); """read port data"""
+        self.phase = Signal(); """even/odd cycle indicator"""
+        self.dbg_a = Signal(addr_width); """debug read port address"""
+        self.dbg_q1 = Signal(data_width); """debug read port data (1st mem)"""
+        self.dbg_q2 = Signal(data_width); """debug read port data (2nd mem)"""
 
     def elaborate(self, _):
         m = Module()