X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimple%2Fissuer.py;h=379c373e99de9a8116298a25e17d95f5087a816b;hb=40fd5c0dd27fd8b586a14531eaa1bd7414132cf1;hp=06bfcdf3de19d13c45a7c3be60d010ed16b04e1a;hpb=265c6ea8ac681d82d4d12f26389d26beb5060f9b;p=soc.git

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 06bfcdf3..379c373e 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -462,12 +462,13 @@ class TestIssuerBase(Elaboratable):
         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 
         # temporary hack: says "go" immediately for both address gen and ST
+        # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
         l0 = core.l0
         ldst = core.fus.fus['ldst0']
         st_go_edge = rising_edge(m, ldst.st.rel_o)
         # link addr-go direct to rel
         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o)
-        m.d.comb += ldst.st.go_i.eq(st_go_edge)  # link store-go to rising rel
+        m.d.sync += ldst.st.go_i.eq(st_go_edge)  # link store-go to rising rel
 
     def do_dmi(self, m, dbg):
         """deals with DMI debug requests