X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimple%2Fissuer_verilog.py;h=dd7bcc773950a296f005559b388fb32c8ffb77f3;hb=6828f2a2930ffd8f3ba4a6aee75315972d856a56;hp=1ddc42114ebef37adbfb113478ec2ffdaeb35274;hpb=870738bcf71053f9533087ce67a1a7c2742b4b6d;p=soc.git

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 1ddc4211..dd7bcc77 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -59,7 +59,7 @@ if __name__ == '__main__':
     parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
                         help="disable SVP64",
                         default=False)
-    parser.add_argument("--pc-reset", default=0,
+    parser.add_argument("--pc-reset", default="0",
                         help="Set PC at reset (default 0)")
     parser.add_argument("--xlen", default=64, type=int,
                         help="Set register width [default 64]")