X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fspec%2Fjtag.py;h=efda2806c07e6f01f3e8501e9bcdd8245fc63991;hb=8c4b4f2411f621e0e69d30f632a8cccd655781e4;hp=f5feec50beca142b854cf4f5ae5dac1d3a2834ee;hpb=ea67c3afe4a77b209c1000012caf14b6c1d2bf3f;p=pinmux.git

diff --git a/src/spec/jtag.py b/src/spec/jtag.py
index f5feec5..efda280 100644
--- a/src/spec/jtag.py
+++ b/src/spec/jtag.py
@@ -15,6 +15,12 @@ iotypes = {'-': IOType.In,
            '*': IOType.InTriOut,
         }
 
+resiotypes = {'i': IOType.In,
+           'o': IOType.Out,
+           'oe': IOType.TriOut,
+           'io': IOType.InTriOut,
+        }
+
 scanlens = {IOType.In: 1,
            IOType.Out: 1,
            IOType.TriOut: 2,
@@ -30,13 +36,16 @@ def dummy_pinset():
              'gpio': gpios,
              'i2c': ['sda*', 'scl+']}
 
+
 # TODO: move to suitable location
 class Pins:
     """declare a list of pins, including name and direction.  grouped by fn
     the pin dictionary needs to be in a reliable order so that the JTAG
     Boundary Scan is also in a reliable order
     """
-    def __init__(self, pindict):
+    def __init__(self, pindict=None):
+        if pindict is None:
+            pindict = {}
         self.io_names = OrderedDict()
         if isinstance(pindict, OrderedDict):
             self.io_names.update(pindict)
@@ -68,13 +77,13 @@ class JTAG(TAP, Pins):
 
         # enumerate pin specs and create IOConn Records.
         # we store the boundary scan register offset in the IOConn record
-        self.ios = [] # these are enumerated in external_ports
+        self.ios = {} # these are enumerated in external_ports
         self.scan_len = 0
         for fn, pin, iotype, pin_name, scan_idx in list(self):
             io = self.add_io(iotype=iotype, name=pin_name)
             io._scan_idx = scan_idx # hmm shouldn't really do this
             self.scan_len += scan_idx # record full length of boundary scan
-            self.ios.append(io)
+            self.ios[pin_name] = io
 
         # this is redundant.  or maybe part of testing, i don't know.
         self.sr = self.add_shiftreg(ircode=4, length=3,
@@ -125,7 +134,7 @@ class JTAG(TAP, Pins):
         """
         ports = super().external_ports()           # gets JTAG signal names
         ports += list(self.wb.fields.values())     # wishbone signals
-        for io in self.ios:
+        for io in self.ios.values():
             ports += list(io.core.fields.values()) # io "core" signals
             ports += list(io.pad.fields.values())  # io "pad" signals"
         return ports