X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fspec%2Fpinfunctions.py;h=bafc09961b6eeeeb39728eaa7c2ae5e049b0bcea;hb=57fd225e5963fc9beba132e3a200c92f2a67913a;hp=57611869913bfa989487e238a425182fc120858f;hpb=9978b689e575433a9e671dc95780caccda4700d0;p=pinmux.git

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 5761186..bafc099 100644
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -95,7 +95,7 @@ def i2c(suffix, bank):
 
 
 def jtag(suffix, bank):
-    return (['TMS+', 'TDI-', 'TDO+', 'TCK+'], [])
+    return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
 
 
 def uart(suffix, bank):
@@ -144,7 +144,8 @@ def flexbus1(suffix, bank):
     for i in range(2):
         buspins.append("CS%d+" % i)
     buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
-                'TS+', 'TBST+',
+                # 'TS+',  commented out for now, mirrors ALE, for mux'd mode
+                'TBST+',
                 'TSIZ0+', 'TSIZ1+']
     for i in range(4):
         buspins.append("BWE%d+" % i)
@@ -163,33 +164,45 @@ def flexbus2(suffix, bank):
 def sdram1(suffix, bank):
     buspins = []
     inout = []
-    for i in range(16):
+    for i in range(8):
         pname = "SDRDQM%d*" % i
         buspins.append(pname)
+    for i in range(8):
+        pname = "SDRD%d*" % i
+        buspins.append(pname)
         inout.append(pname)
     for i in range(12):
         buspins.append("SDRAD%d+" % i)
-    for i in range(8):
-        buspins.append("SDRDQ%d+" % i)
-    for i in range(3):
-        buspins.append("SDRCS%d#+" % i)
-    for i in range(2):
-        buspins.append("SDRDQ%d+" % i)
     for i in range(2):
         buspins.append("SDRBA%d+" % i)
-    buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
-                'SDRRST+']
+    buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
+                'SDRCSn0++']
     return (buspins, inout)
 
 
 def sdram2(suffix, bank):
     buspins = []
     inout = []
-    for i in range(3, 6):
-        buspins.append("SDRCS%d#+" % i)
-    for i in range(16, 32):
+    for i in range(1, 6):
+        buspins.append("SDRCSn%d+" % i)
+    for i in range(8, 16):
         pname = "SDRDQM%d*" % i
         buspins.append(pname)
+    for i in range(8, 16):
+        pname = "SDRD%d*" % i
+        buspins.append(pname)
+        inout.append(pname)
+    return (buspins, inout)
+
+
+def sdram3(suffix, bank):
+    buspins = []
+    inout = []
+    for i in range(12, 13):
+        buspins.append("SDRAD%d+" % i)
+    for i in range(8, 64):
+        pname = "SDRD%d*" % i
+        buspins.append(pname)
         inout.append(pname)
     return (buspins, inout)
 
@@ -256,6 +269,7 @@ pinspec = (('IIS', i2s),
            ('FB', flexbus2),
            ('SDR', sdram1),
            ('SDR', sdram2),
+           ('SDR', sdram3),
            ('EINT', eint),
            ('PWM', pwm),
            ('GPIO', gpio),