X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fspec%2Fpinfunctions.py;h=bafc09961b6eeeeb39728eaa7c2ae5e049b0bcea;hb=57fd225e5963fc9beba132e3a200c92f2a67913a;hp=985dfd7c21c7b2d88fbf9f3946b22d71f5774907;hpb=b58cfb6cd55974645e52ef281fd81581b3809da8;p=pinmux.git diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index 985dfd7..bafc099 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -61,8 +61,11 @@ def sdmmc(suffix, bank): return emmc(suffix, bank, pincount=4) -def nspi(suffix, bank, iosize): - qpins = ['CK*', 'NSS*'] +def nspi(suffix, bank, iosize, masteronly=True): + if masteronly: + qpins = ['CK+', 'NSS+'] + else: + qpins = ['CK*', 'NSS*'] inout = [] for i in range(iosize): pname = "IO%d*" % i @@ -70,6 +73,15 @@ def nspi(suffix, bank, iosize): inout.append(pname) return (qpins, inout) + +def mspi(suffix, bank): + return nspi(suffix, bank, 2, masteronly=True) + + +def mquadspi(suffix, bank): + return nspi(suffix, bank, 4, masteronly=True) + + def spi(suffix, bank): return nspi(suffix, bank, 2) @@ -83,7 +95,7 @@ def i2c(suffix, bank): def jtag(suffix, bank): - return (['TMS+', 'TDI-', 'TDO+', 'TCK+'], []) + return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], []) def uart(suffix, bank): @@ -131,11 +143,12 @@ def flexbus1(suffix, bank): inout.append(pname) for i in range(2): buspins.append("CS%d+" % i) - buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+', - 'A0', 'A1', 'TS', 'TBST', - 'TSIZ0', 'TSIZ1'] + buspins += ['ALE+', 'OE+', 'RW+', 'TA-', + # 'TS+', commented out for now, mirrors ALE, for mux'd mode + 'TBST+', + 'TSIZ0+', 'TSIZ1+'] for i in range(4): - buspins.append("BWE%d" % i) + buspins.append("BWE%d+" % i) for i in range(2, 6): buspins.append("CS%d+" % i) return (buspins, inout) @@ -151,33 +164,45 @@ def flexbus2(suffix, bank): def sdram1(suffix, bank): buspins = [] inout = [] - for i in range(16): + for i in range(8): pname = "SDRDQM%d*" % i buspins.append(pname) + for i in range(8): + pname = "SDRD%d*" % i + buspins.append(pname) inout.append(pname) for i in range(12): buspins.append("SDRAD%d+" % i) - for i in range(8): - buspins.append("SDRDQ%d+" % i) - for i in range(3): - buspins.append("SDRCS%d#+" % i) - for i in range(2): - buspins.append("SDRDQ%d+" % i) for i in range(2): buspins.append("SDRBA%d+" % i) - buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+', - 'SDRRST+'] + buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+', + 'SDRCSn0++'] return (buspins, inout) def sdram2(suffix, bank): buspins = [] inout = [] - for i in range(3, 6): - buspins.append("SDRCS%d#+" % i) - for i in range(16, 32): + for i in range(1, 6): + buspins.append("SDRCSn%d+" % i) + for i in range(8, 16): pname = "SDRDQM%d*" % i buspins.append(pname) + for i in range(8, 16): + pname = "SDRD%d*" % i + buspins.append(pname) + inout.append(pname) + return (buspins, inout) + + +def sdram3(suffix, bank): + buspins = [] + inout = [] + for i in range(12, 13): + buspins.append("SDRAD%d+" % i) + for i in range(8, 64): + pname = "SDRD%d*" % i + buspins.append(pname) inout.append(pname) return (buspins, inout) @@ -229,6 +254,8 @@ def gpio(suffix, bank): pinspec = (('IIS', i2s), ('MMC', emmc), ('SD', sdmmc), + ('MSPI', mspi), + ('MQSPI', mquadspi), ('SPI', spi), ('QSPI', quadspi), ('TWI', i2c), @@ -242,6 +269,7 @@ pinspec = (('IIS', i2s), ('FB', flexbus2), ('SDR', sdram1), ('SDR', sdram2), + ('SDR', sdram3), ('EINT', eint), ('PWM', pwm), ('GPIO', gpio),