X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fspec%2Fpinfunctions.py;h=c09eb1cff771fe26ad9f2dc113adf05f70b832c8;hb=990e85b3f76ecf56e7d9e6a458028ff242573b50;hp=0a8d7bbadd5efb59af199eea7dd458ad56684959;hpb=19a02e38b01d9acd642da277babb6e0b3b361057;p=pinmux.git diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index 0a8d7bb..c09eb1c 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -2,8 +2,10 @@ """ define functions here, with their pin names and the pin type. - each function returns a list (or an object with a __getitem__ function) - containing pin name plus type specifications. + each function returns a pair of lists + (or objects with a __getitem__ function) + + the first list (or object) contains pin name plus type specifications. the type is: @@ -25,63 +27,98 @@ generated, and that's not known immediately (or it would be if every single one of the functions below had a start and end parameter added). see spec.interfaces.PinGen class slice on pingroup + + the second list is the names of pins that are part of an inout bus. + this list of pins (a ganged group) will need to be changed under + the control of the function, as a group. for example: sdmmc's + D0-D3 pins are in-out, they all change from input to output at + the same time under the control of the function, therefore there's + no point having multiple in-out switch/control wires, as the + sdmmc is never going to do anything other than switch this entire + bank all at once. so in this particular example, sdmmc returns: + + (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names + ['D0*', 'D1*', 'D2*', 'D3*']) # ganged bus names """ def i2s(suffix, bank): - return ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'] + return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'], + []) -def emmc(suffix, bank): +def emmc(suffix, bank, pincount=8): emmcpins = ['CMD+', 'CLK+'] - for i in range(8): - emmcpins.append("D%d*" % i) - return emmcpins + inout = [] + for i in range(pincount): + pname = "D%d*" % i + emmcpins.append(pname) + inout.append(pname) + return (emmcpins, inout) def sdmmc(suffix, bank): - sdmmcpins = ['CMD+', 'CLK+'] - for i in range(4): - sdmmcpins.append("D%d*" % i) - return sdmmcpins + return emmc(suffix, bank, pincount=4) + + +def nspi(suffix, bank, iosize, masteronly=True): + if masteronly: + qpins = ['CK+', 'NSS+'] + else: + qpins = ['CK*', 'NSS*'] + inout = [] + for i in range(iosize): + pname = "IO%d*" % i + qpins.append(pname) + inout.append(pname) + return (qpins, inout) + + +def mspi(suffix, bank): + return nspi(suffix, bank, 2, masteronly=True) + + +def mquadspi(suffix, bank): + return nspi(suffix, bank, 4, masteronly=True) def spi(suffix, bank): - return ['CLK*', 'NSS*', 'MOSI*', 'MISO*'] + return nspi(suffix, bank, 2) def quadspi(suffix, bank): - return ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*'] + return nspi(suffix, bank, 4) def i2c(suffix, bank): - return ['SDA*', 'SCL*'] + return (['SDA*', 'SCL*'], []) def jtag(suffix, bank): - return ['MS+', 'DI-', 'DO+', 'CK+'] + return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], []) def uart(suffix, bank): - return ['TX+', 'RX-'] + return (['TX+', 'RX-'], []) def ulpi(suffix, bank): ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+'] for i in range(8): ulpipins.append('D%d*' % i) - return ulpipins + return (ulpipins, []) def uartfull(suffix, bank): - return ['TX+', 'RX-', 'CTS-', 'RTS+'] + return (['TX+', 'RX-', 'CTS-', 'RTS+'], + []) def rgbttl(suffix, bank): ttlpins = ['CK+', 'DE+', 'HS+', 'VS+'] for i in range(24): - ttlpins.append("D%d+" % i) - return ttlpins + ttlpins.append("OUT%d+" % i) + return (ttlpins, []) def rgmii(suffix, bank): @@ -94,64 +131,89 @@ def rgmii(suffix, bank): 'EMDC+', 'EMDIO*', 'ETXEN+', 'ETXCK+', 'ECRS-', 'ECOL+', 'ETXERR+'] - return buspins + return (buspins, []) def flexbus1(suffix, bank): buspins = [] + inout = [] for i in range(8): - buspins.append("AD%d*" % i) + pname = "AD%d*" % i + buspins.append(pname) + inout.append(pname) for i in range(2): buspins.append("CS%d+" % i) - buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+', - 'A0', 'A1', 'TS', 'TBST', - 'TSIZ0', 'TSIZ1'] + buspins += ['ALE+', 'OE+', 'RW+', 'TA-', + # 'TS+', commented out for now, mirrors ALE, for mux'd mode + 'TBST+', + 'TSIZ0+', 'TSIZ1+'] for i in range(4): - buspins.append("BWE%d" % i) + buspins.append("BWE%d+" % i) for i in range(2, 6): buspins.append("CS%d+" % i) - return buspins + return (buspins, inout) def flexbus2(suffix, bank): buspins = [] for i in range(8, 32): buspins.append("AD%d*" % i) - return buspins + return (buspins, buspins) def sdram1(suffix, bank): buspins = [] - for i in range(16): - buspins.append("SDRDQM%d*" % i) + inout = [] + for i in range(8): + pname = "SDRDQM%d*" % i + buspins.append(pname) + for i in range(8): + pname = "SDRD%d*" % i + buspins.append(pname) + inout.append(pname) for i in range(12): buspins.append("SDRAD%d+" % i) - for i in range(8): - buspins.append("SDRDQ%d+" % i) - for i in range(3): - buspins.append("SDRCS%d#+" % i) - for i in range(2): - buspins.append("SDRDQ%d+" % i) for i in range(2): buspins.append("SDRBA%d+" % i) - buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+', - 'SDRRST+'] - return buspins + buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+', + 'SDRCSn0+'] + return (buspins, inout) def sdram2(suffix, bank): buspins = [] - for i in range(3, 6): - buspins.append("SDRCS%d#+" % i) - for i in range(8, 32): - buspins.append("SDRDQ%d*" % i) - return buspins + inout = [] + for i in range(1, 6): + buspins.append("SDRCSn%d+" % i) + for i in range(8, 16): + pname = "SDRDQM%d*" % i + buspins.append(pname) + for i in range(8, 16): + pname = "SDRD%d*" % i + buspins.append(pname) + inout.append(pname) + return (buspins, inout) + + +def sdram3(suffix, bank): + buspins = [] + inout = [] + for i in range(12, 13): + buspins.append("SDRAD%d+" % i) + for i in range(8, 64): + pname = "SDRD%d*" % i + buspins.append(pname) + inout.append(pname) + return (buspins, inout) def mcu8080(suffix, bank): buspins = [] + inout = [] for i in range(8): - buspins.append("MCUD%d*" % i) + pname = "MCUD%d*" % i + buspins.append(pname) + inout.append(pname) for i in range(8): buspins.append("MCUAD%d+" % (i + 8)) for i in range(6): @@ -160,7 +222,7 @@ def mcu8080(suffix, bank): buspins.append("MCUNRB%d+" % i) buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+', 'MCURST+'] - return buspins + return (buspins, inout) class RangePin(object): @@ -176,15 +238,15 @@ class RangePin(object): def eint(suffix, bank): - return RangePin("*") + return (RangePin("-"), []) def pwm(suffix, bank): - return RangePin("+") + return (RangePin("+"), []) def gpio(suffix, bank): - return ("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")) + return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), []) # list functions by name here @@ -192,12 +254,14 @@ def gpio(suffix, bank): pinspec = (('IIS', i2s), ('MMC', emmc), ('SD', sdmmc), + ('MSPI', mspi), + ('MQSPI', mquadspi), ('SPI', spi), ('QSPI', quadspi), ('TWI', i2c), ('JTAG', jtag), ('UART', uart), - ('UARTQ', uartfull), + ('QUART', uartfull), ('LCD', rgbttl), ('ULPI', ulpi), ('RG', rgmii), @@ -205,6 +269,7 @@ pinspec = (('IIS', i2s), ('FB', flexbus2), ('SDR', sdram1), ('SDR', sdram2), + ('SDR', sdram3), ('EINT', eint), ('PWM', pwm), ('GPIO', gpio),