X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fspec%2Fpinfunctions.py;h=c09eb1cff771fe26ad9f2dc113adf05f70b832c8;hb=990e85b3f76ecf56e7d9e6a458028ff242573b50;hp=423a190159dc462d499a8bcfb3f7ce138c977fc7;hpb=20d1d0d0616bc0ede3236f40f120393e7fdc89ef;p=pinmux.git diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index 423a190..c09eb1c 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -164,33 +164,45 @@ def flexbus2(suffix, bank): def sdram1(suffix, bank): buspins = [] inout = [] - for i in range(16): + for i in range(8): pname = "SDRDQM%d*" % i buspins.append(pname) + for i in range(8): + pname = "SDRD%d*" % i + buspins.append(pname) inout.append(pname) for i in range(12): buspins.append("SDRAD%d+" % i) - for i in range(8): - buspins.append("SDRDQ%d+" % i) - for i in range(3): - buspins.append("SDRCS%d#+" % i) - for i in range(2): - buspins.append("SDRDQ%d+" % i) for i in range(2): buspins.append("SDRBA%d+" % i) - buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+', - 'SDRRST+'] + buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+', + 'SDRCSn0+'] return (buspins, inout) def sdram2(suffix, bank): buspins = [] inout = [] - for i in range(3, 6): - buspins.append("SDRCS%d#+" % i) - for i in range(16, 32): + for i in range(1, 6): + buspins.append("SDRCSn%d+" % i) + for i in range(8, 16): pname = "SDRDQM%d*" % i buspins.append(pname) + for i in range(8, 16): + pname = "SDRD%d*" % i + buspins.append(pname) + inout.append(pname) + return (buspins, inout) + + +def sdram3(suffix, bank): + buspins = [] + inout = [] + for i in range(12, 13): + buspins.append("SDRAD%d+" % i) + for i in range(8, 64): + pname = "SDRD%d*" % i + buspins.append(pname) inout.append(pname) return (buspins, inout) @@ -257,6 +269,7 @@ pinspec = (('IIS', i2s), ('FB', flexbus2), ('SDR', sdram1), ('SDR', sdram2), + ('SDR', sdram3), ('EINT', eint), ('PWM', pwm), ('GPIO', gpio),