X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fspec%2Ftesting_stage1.py;h=aa888079645612c726fda6912f5b2d2a71411e87;hb=e773400775f479a98f9dc527e54884e096113691;hp=ec9eff181f7cf8a7dcac75ba7873b8de1ac8aeb7;hpb=05c2303211b356eeb88168084e93e4b0b7897205;p=pinmux.git

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index ec9eff1..aa88807 100644
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -408,10 +408,20 @@ def test_case0():
     yield Delay(delayVal)
     yield Settle()
     for _ in range(20):
-        yield top.gpio.gpio2.o.eq(~top.gpio.gpio2.o)
+        # get a value first (as an integer).  you were trying to set
+        # it to the actual Signal
+        gpio_o2 = yield top.gpio.gpio2.o
+        # then set it
+        yield top.gpio.gpio2.o.eq(~gpio_o2)
+
+        # ditto: here you are trying to set to an AST expression
+        # which is inadviseable (likely to fail)
         yield top.gpio.gpio3.o.eq(~top.gpio.gpio3.o)
         yield Delay(delayVal)
         yield Settle()
+        # again you are trying to set something equal to the Signal
+        # rather than to a value.  this is attempting to change the
+        # actual HDL which is completely inappropriate
         yield top.uart.rx.eq(~top.intermediary)
         yield Delay(delayVal)
         yield Settle()