Rework SOC reset
authorAnton Blanchard <anton@linux.ibm.com>
Sat, 7 Sep 2019 11:28:21 +0000 (21:28 +1000)
committerAnton Blanchard <anton@ozlabs.org>
Sat, 7 Sep 2019 21:40:19 +0000 (07:40 +1000)
commit03fd06deaf9f12725696c5769a469f5fcbdc9aa2
tree2063215db29c39aa51203718999eebce0cb78b0d
parenta53ad600145f04348f8270c82dcb3979341c8368
Rework SOC reset

The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:

- Wait a number of external clock cycles before removing reset from
  the PLL.

- After the PLL locks and the external reset button isn't pressed,
  wait a number of PLL clock cycles before removing reset from the SOC.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Makefile
fpga/clk_gen_bypass.vhd
fpga/clk_gen_plle2.vhd
fpga/pp_soc_reset.vhd [deleted file]
fpga/soc_reset.vhdl [new file with mode: 0644]
fpga/soc_reset_tb.vhdl [new file with mode: 0644]
fpga/toplevel.vhd
microwatt.core